In recent years, copper materials have found increasing use in semiconductor manufacturing technologies. Such methods commonly include the so-called damascene and dual-damascene manufacturing processes. Generally, such processes generally involve forming openings in a process layer, filling the layer with copper, and then planarizing the surface to complete the process. In one common implementation, such damascene (and dual damascene) processes are used to interconnect the metallization layers of multi-layer semiconductor structures.
Briefly, a metallization layer is formed on a semiconductor substrate (e.g. a wafer or semiconductor die) in accordance with metallization processes known in the art. The metallization layer includes patterns of circuit paths and electrical connections. In multi-layer structures, the circuit patterns of one metallization layer are electrically connected to circuit patterns formed on other metallization layers formed above and below the layer in question. Typically, the metallization layers are separated by one or more layers of dielectric material. These intervening layers are collectively referred to as the inter-layer dielectric (ILD) layer. Electrical interconnections between the metallization layers are commonly made by forming vias through the ILD, and filling the vias with copper materials.
As is known to those having ordinary skill in the art, when copper materials are used, metal barrier layers are needed to prevent copper from diffusing into the ILD layer and “poisoning” the ILD. Commonly, such metal barrier materials comprise metals or metal compounds (e.g., TiN, TaN, and other metal containing barrier materials). Such materials form excellent barriers to copper diffusion. FIG. 1 illustrates one particular application of conventional metal barrier layers as currently used. The depicted structure is a cross-section schematic view of a portion of a semiconductor substrate. A copper conducting line 102 of the metallization layer is shown formed in a silicon layer 101. Overlying the silicon layer 101 and metallization layer is an ILD layer 103 formed of dielectric materials. In a multi-layer structure, subsequent metallization layers are commonly formed on top of the ILD layer 103. In order to establish electrical connection between the layers, conductive vias can be used. Such vias can be formed by creating an opening 104 in the ILD layer 103 and then creating a conductive interconnect therein. In the depicted implementation, the opening 104 includes a metal barrier layer 105 formed on the walls of the opening. Additionally, such metal barrier layers 105 typically cover the underlying copper conducting line 102. Once the metal barrier layer 105 is formed, a copper interconnect (plug) 106 is typically deposited over the metal barrier layers 105 in the opening 104 to form a copper interconnect. The surface can then be planarized (e.g., using CMP) to prepare the surface for further processing. Such structures find wide usage and applicability in current semiconductor fabrication.
Such metal barrier layer and via structures are satisfactory for many applications. However, as critical dimensions decrease, especially below the 1μ (micron) level, the proportion of space in the via occupied by the metal barrier layer 105 becomes greater and greater. This results in less room in the via for the highly conductive copper interconnect 106. Because copper is significantly more conductive than existing metal barrier layers, the overall conductivity of an interconnect is significantly reduced as the proportion of metal barrier layer material goes up. This is especially so in conductive vias having diameters of 1μ or less. Moreover, in existing processes the metal barrier layer 105 extends across the bottom of the via 105b. The interfaces between copper (e.g., 102 and 106) and the bottom portion 105b of the metal barrier layer are subject to a high incidence of failure.
Thus, for these and other reasons, there is a need for improvements in copper barrier layer structures.